1. Field of the Invention
The present invention relates to electrically programmable read only memory (EPROM) devices and, in particular, to a contactless flash EPROM cell array that utilizes a low current channel erase mechanism.
2. Discussion of the Prior Art
FIG. 1 shows a portion of Intel's well-known ETOX EPROM array 10 wherein two ETOX cells 12a and 12b share one drain contact 14. FIG. 2 shows a cross-section of an individual ETOX cell 12 taken along line A--A (i.e. along polysilicon (poly 2) word line 16) in FIG. 1. FIG. 3 shows a cross-section of an ETOX cell 12 taken along line B--B (i.e. along buried N+ bit line 18) in FIG. 1.
The ETOX array 10 is based on the standard "T-shaped" ETOX cell. As shown in FIGS. 2 and 3, the ETOX cell 12 is implemented utilizing a very thin gate oxide 20 (about 100 .ANG.) and graded N+/N- source regions 22 to prevent disturbances due to junction breakdown when the cell 12 is being erased.
As shown in FIG. 4A, the ETOX cell is written in the conventional EPROM manner. That is, hot electrons are injected from the graded source region 22 into the polysilicon (poly1) floating gate 24 when the poly 2 word line 16 and the N+ bit line (drain) 14 are both high.
As shown in FIG. 4B, erasing the ETOX cell 12 is performed by Fowler-Nordheim tunneling of electrons from the floating gate 24 through the thin oxide 20 to the graded source region 22 when the source region 22 is high, the drain 14 is floating and the word line 16 is low. As stated above, the source 22 is graded to prevent junction breakdown during the erase operation.
As discussed by Verma et al., "Reliability Performance of ETOX Based Flash Memories", the programming of flash EPROM cells, such as the above-described ETOX cell, may cause certain cell disturbances. Thus, an important consideration in the design of flash EPROM cells is the proper selection of read and programming voltages in order to minimize these disturbs.
Furthermore, the above-described ETOX array utilizes a cell architecture that requires one drain contact for every two cells in the array. The relatively large size of the contacts places a severe scaling limitation on the array.
U.S. patent application Ser. No. 539,657, filed by Boaz Eitan on Jun. 13, 1990, titled EPROM VIRTUAL GROUND ARRAY, discloses a so-called "contactless" alternate metal virtual ground (AMG) EPROM cell array and its associated process flow. Eitan's AMG concept is attractive because it allows high density EPROMs to be fabricated without using aggressive fabrication technologies and design rules.
As shown in FIGS. 5 and 6, the basic idea of the Eitan array 30 is the use of a "cross-point" EPROM cell that is defined by the crossing of perpendicular poly1 floating gate lines 32 and poly2 word lines 34 in a virtual ground array. To avoid drain turn-on, i.e. electron leakage from unselected cells on the same bit line as a selected cell, metal 36 contacts silicon every two N.sup.+ bit lines 38 to define the drain lines of the array and the non-contacted N.sup.+ bit lines 40 are connected to ground only via access transistors 42 driven by access select lines 44 to define the source lines of the array.
In the Eitan architecture, each drain bit line 38 is contacted only once every 64 cells, each block of 64 cells on the same drain bit line 38 constituting one "segment." Thus, when programming a particular cell in the array 30, only one 64-cell segment need be addressed; all other segments are "off." Therefore, the cells in the unselected segments are not susceptible to leakage.
U.S. patent application Ser. No. 830,938, filed by Albert Bergemont on Feb. 4, 1992, titled ALTERNATE METAL/SOURCE VIRTUAL GROUND FLASH CELL ARRAY, which is commonly-assigned herewith to National Semiconductor Corporation, discloses an AMG flash EPROM array concept.
As shown in FIGS. 7-9, the Bergemont array 50 differs from the Eitan array in two primary aspects. First, alternate N.sup.+ bit lines receive an additional phosphorous implant to provide graded N.sup.+ /N.sup.- source bit lines 52 for the array cells. Furthermore, in a reversal of the Eitan concept, the N.sup.+ /N.sup.- graded source bit lines 52, rather than the N.sup.+ drain bit lines 56, are contacted by metal 54 in segmented fashion; the intermediate node N.sup.+ drain bit lines 56 are noncontacted. As shown in FIG. 8, optionally, the N.sup.+ drain bit lines 56 of the Bergemont array can receive a boron implant to provide N.sup.+ /P.sup.- drain lines 56. The Bergemont array retains the basic "cross-point" cell architecture in that the cells of the array are defined by the perpendicular crossing of poly1 floating gate lines 58 and poly2 word lines 60. Note that, as shown in FIG. 7, the Bergemont cell includes poly1 extensions over field oxide (Fox) in the array in order to achieve a correct coupling from the control gate (i.e. word line 60) to the floating gate 58, particularly in flash applications wherein the thickness of the floating gate oxide is approximately 100.ANG..
The Bergemont architecture facilitates a flash erase mode, wherein an erase voltage is applied to each of the N.sup.+ /N.sup.- source bit lines 52 while both access select lines 62 are held at ground. This causes Fowler-Nordheim tunneling of electrons from the floating gate 58 to the source side 52 of the cell. The graded N.sup.+ /N.sup.- source junction prevents junction breakdown.
The above-described Bergemont AMG flash EPROM array provides a significant advance over the conventional flash ETOX technology by achieving a contactless array. However, like the flash ETOX technology, the double-diffused source lines place a scaling constraint on the effective channel length of the cell.